1. Field of the Invention
The present invention relates to the field of microelectronics and in particular to digital circuits. Still more particularly, the present invention relates to output drivers in digital circuits.
2. Description of the Prior Art
In a digital circuit system, a common path is often used to share and transfer data between various circuits and devices in the system. A small set of shared lines, a bus, may be used to provide the common path. In the designing of digital circuit systems, some devices may have an insufficient amount of maximum output current to drive all of the lines connected to the devices. As a result, a current amplifier, called a driver or a buffer, is used to provide the needed currents.
Latches are often used to control output drivers in digital circuit systems. In some instances it is desirable to enable and disable the output driver. For example, the output driver may be disabled (placed into an open state) so that another logic device may drive the same line that the output driver is connected to. Previously, latches were enabled and disabled using a logic gate placed between the latch and the output driver as shown in FIG. 1.
Referring to FIG. 1, a schematic diagram of a latch controlled output driver 70 known in the prior art is depicted. Latch controlled output driver circuit 70 includes an input circuit 71, a latch circuit 72, an enable/disable circuit 74, and an output driver circuit 76. Input circuit 71 is constructed from pass gates G1 and G2 and inverter I1; latch circuit 72 is constructed from inverters I2-I5. Enable/disable circuit 74 is constructed from NAND gates A1 and A2 and inverters I6 and I7, and output driver circuit 76 includes transistors T1 and T2. Transistor T1 is a pull-up transistor and transistor T2 is a pull-down transistor in the output driver portion of this circuit. Transistors T1 and T2 are n-channel metal-oxide field effect transistors (MOSFETs). The drain of transistor T1 is connected to power supply voltage VCC, and the source of transistor T2 is connected to power supply voltage VSS. Typically, power supply voltage VCC is at a higher voltage than power supply voltage VSS.
Signals are input into latch controlled output driver circuit 70 at inputs GDT and GDC. The gate of transistor T1 is controlled by a signal entering the latch controlled output driver at input GDT; the gate of transistor T2 is controlled by a signal entering the latch controlled output driver 70 at input GDC. Pass gates G1 and G2 control the flow of the signal from inputs GDT and GDC to output driver circuit 76. Pass gates G1 and G2 are controlled by a clock signal, CLK applied to point 80 and a complement clock signal, /CLK, which is generated by passing the clock signal through inverter I1.
Referring back to latch circuit 72, inverters I2 and I3 are cross-coupled; inverters I4 and I5 are cross-coupled. When pass gates G1 and G2 are turned off, inverters I2-I5 provide the latching mechanism to provide a continuous signal to the gates of transistor T1 and T2 when output driver circuit 76 is enabled by enable/disable circuit 74.
NAND gates A1 and A2 in enable/disable circuit 74 are employed to enable and disable output driver circuit 76. Signals from input points GDT and GDC are allowed to travel through NAND gates A1 and A2 to the gates of transistors T1 and T2 when the signal at inputs OE are a logic one. In the situation, where the signal at inputs OE is a logic zero, the latch controlled output circuit 70 is disabled, both transistors are off, and the output of output driver circuit 76 is a high Z.
The addition of the NAND gates and inverters to provide an enable/disable function in latch controlled output driver 70 in FIG. 1 increases the response time of the latch controlled output driver. Therefore, it would be desirable to have an apparatus to decrease the time needed to enable and disable a latch controlled output driver.